Exemplary embodiments relate to a high voltage control circuit of a semiconductor device and, more particularly, to a high voltage control circuit of a semiconductor device which can be driven at a relatively low voltage.
A semiconductor device requires higher pumping voltage than an input power supply voltage, and a high voltage control circuit is required in order to transfer the voltage to pertinent circuits or elements.
FIG. 1 is a circuit diagram of a known high voltage control circuit of a semiconductor device.
Referring to FIG. 1, when an operation of transmitting a high voltage is performed, inverters IV1 and IV2 buffer an input signal A of a high logic level and output the buffered signal as a signal of a high logic level. An NMOS transistor NMOS and a high voltage NMOS transistor HNMOS transmit a signal of a high logic level, outputted from the inverter IV2, to an output terminal NA in response to a first control signal B. Accordingly, the potential of the output terminal NA rises by a potential of the signal of a high logic level. A second control signal C outputted from the inverter IV1 turns on a high voltage PMOS transistor HPMOS. The potential of the output terminal NA is inputted to the gate of a negative voltage transistor NNMOS, which is thus turned on. Accordingly, a high voltage VPP is supplied to the output terminal NA.
When an operation of cutting off the transmission of a high voltage is performed, the inverters IV1 and IV2 buffer the input signal A of a low logic level and output the buffered signal as a signal of a low logic level. The NMOS transistor NMOS and the high voltage NMOS transistor HNMOS are turned on in response to the first control signal B. At this time, the current of the output terminal NA is discharged through the NMOS transistor NMOS, the high voltage NMOS transistor HNMOS, and the inverter IV2.
The known high voltage control circuit is not normally operated in a low voltage device having a power supply voltage of 2.3 V or 1.8 V. This is because in order to turn off the high voltage PMOS transistor HPMOS when the operation of cutting off the transmission of a high voltage is performed, the second control signal C of a high voltage level has to be supplied. Since the second control signal C of 2.3 V or 1.8 V is generated in the low voltage device having the power supply voltage of 2.3 V or 1.8 V, the high voltage PMOS transistor HPMOS is not fully turned off, and some current flows through the high voltage PMOS transistor HPMOS. Accordingly, a potential of 2.5 V or 2.8 V may be transferred to the output terminal NA.